Silicon nanoelectronics: Organized networks

Conventional computer chips are fabricated by photolithography and chemical etching to produce the tiny devices that make up microcircuits. But squeezing even more devices into smaller areas is challenging via this ‘top-down’ approach.

An alternative and potentially more promising procedure is the fabrication of nanoscale device structures based on self-assembly, which involves minimal external manipulation. Such a ‘bottom-up’ approach could enable devices and circuits to be built atom-by-atom. Researchers from the National Chiayi University in Taiwan¹ have now discovered a self-organization process that can be used to form an ultra-dense two-dimensional network of well-ordered silicon nanowires. 

Fig. 1: Scanning tunnelling microscope image of a mesh of silicon nanowires that spontaneously self-assemble on a silicon (110) surface when heated to 750 °C for 60 min and then 600 °C for 30 min.

This approach is based on a phenomenon known as surface diffusion. When a highly crystalline wafer having a surface with periodic domain structures is heated beyond a certain temperature, the atoms on the surface become mobile and diffuse along certain domain orientations. Consequently, periodically ordered nanostructure arrays can be formed on the surface of the wafer. The researchers found that when a silicon (110) surface with two non-orthogonal grating-like superstructures was heated in a series of prolonged annealing steps, the two domain structures of parallel terraces extended and eventually intersected with each other to form a regular mesh of criss-crossing silicon nanowires (Fig. 1).

“The silicon nanomesh could be used as a means of building ultrahigh-density molecular electronic memory circuits by inserting functional organic molecules into the junctions where the silicon nanowires intersect to function as the basis of a nanowire memory unit,” says Ie-Hong Hong from the research group.

If such ideas could be implemented, it could lead to a significant increase in the number of discrete devices that could be integrated on a silicon chip. With conventional technology, around one billion transistors can be grown per square centimeter of silicon wafer. In comparison, the density of junctions between the nanowires grown by Hong and his colleagues exceeds one trillion junctions per square centimeter.  

In the future, the researchers hope to use these nanowire meshes as templates for the growth of metal and organic structures, which could both be useful in their own right but which will also be an important next step towards the self-assembly-based construction of integrated, functional crossbar nanomeshes.

Reference

1. Hong, I-.H.,* Liao, Y-.C. & Yen, S-.C. Self-organization of a highly integrated silicon nanowire network on a Si(110)-16x2 surface by controlled domain growth. Adv. Funct. Mater.  19, 3389 (2009).  | article

Author affiliation

Institute of Optoelectronics and Solid State Electronics, National Chiayi University, Chiayi 60004, Taiwan
*Email: ihhong@mail.ncyu.edu.tw

Source: https://secure.natureasia.com/asia-materials/highlight.php?id=582