Silicon nanoelectronics. Physics of Silicon Nanodevices. Practical CMOS Scaling. The Scaling Limit of MOSFETs due to Direct. Quantum Effects in Silicon Nanodevices. Ballistic Transport in Silicon Nanostructures. Resonant Tunneling in Si Nanodevices. Silicon Single-Electron Transistor and Memory. Silicon Memories Using Quantum and Single-Electron Effects. SESO Memory Devices. Few Electron Devices and Memory Circuits. Single-Electron Logic Devices.
Silicon Memories Using Quantum and Single-Electron Effects
Nearly four decades ago, Neugebauer and Webb1 recognized that when capacitance is reduced, the electrostatic energy required to charge the capacitance (e2/2C) can be made to be of the order of magnitude of thermal voltage (10s of meV) at dimensions in the 10-nm range which results in a capacitance in the aF (10-18 F) range. This implies that discrete single-electron transmission or storage events can be observed, and unless the electrostatic energy is available to the electron from an energy source such as a power supply, the transition is prohibited. This is known as Coulomb blockade. Figure 8.1 shows an illustrative schematic, with band-diagrams for such a confined system. For a confined system in a semiconductor, quantum effects can also be significant due to a reduced number of states. In three-dimensionally confined semiconductor structures, the order of magnitude of the confinement energy can be similar to that due to Coulomb blockade. Fulton and Dolan,in 1987, demonstrated the first single-electron transistor by showing the modulation of the Coulomb blockade region by an applied bias voltage, and in recent times, there has been tremendous interest in understanding of this mesoscopic system,From a device point of view, an important consequence of the use of single-electron and quantum effects is the reduction in the number of charged carriers. Reduction of the number of charged carriers used in the operation of devices results in low power consumption and for some device examples increased reliability by reducing the total energy per operation. However, the reduction of the number of electrons is not without changes in properties whose reproducibility microelectronics has taken advantage of. One is a reduction in the "collective phenomena" that we have relied on to achieve reproducibility in microelectronics. Examples of such collective phenomena are the number of electrons flowing through the channel, the number of electrons transferred during a CMOS switching event, and the number of dopants used to control the threshold voltage. A smaller number of electrons leads to larger fluctuations in the current, a smaller number of electrons transferred during switching leads to larger fluctuations in the switching voltage levels or time constants, and a smaller number of dopants leads to larger fluctuations in the threshold voltage or equivalent parameters. Small dimensions are not easy to achieve, and hence many implementations of single-electron devices suffer from reduced gain, voltages needed, and temperatures at which the phenomena can be observed unambiguously. We will discuss these in the context of the operation of these devices and limitations of CMOS with which they usually need to be integrated. And, in particular, we will focus on the attributes of devices that are formed as flash memory structures.
MEMORIES BY SCALING FLOATING GATES OF
Coupling the discrete electron effects to the channel of a field-effect transistor has resulted in a number of successes in using single-electron effects at room temperature. There are a number of interesting examples of this approach. Yano et al.13 used a thin polygrain silicon film, in which current flows through a series of connected grains with conduction constrained by presence of electrons on a grain that is separated from, but in close proximity to, the channel. Another example of such a coupled-channel approach is scaling of the floating gate region of a flash memory to dimensions where the discreteness effects become strong. Nanocrystal memories14–17 (Figure 8.5) accomplish this through a distribution of quantum dots, while quantum-dot memories18,19 (Figure 8.6) accomplish this by scaling the entire device geometry to the ultrasmall dimensions. Both are examples of flash memories that utilize quantum dot(s) between the gate and the channel of a field-effect transistor to store electrons, which screen the mobile charge in the channel, thus inducing a change in the threshold voltage or conductivity of the underlying channel. These quantum dots are transmissively coupled to the channel and isolated from the gate, and their processing can be accomplished together with CMOS processing. Their reduced dimension and confinement brings forth two important features that are absent in the conventional floating gate structures: a reduced density of states that restricts the states available for electrons and holes to tunnel, and the Coulomb blockade effect that arises from a larger electrostatic energy associated with placing a charged particle onto a smaller capacitance. In a floating-gate memory, when the gate energy is lowered with regard to that of the source and the drain, electrons transfer to the floating gate storage nodes. For nanocrystal memories, these storage nodes are small single-crystal silicon islands (nanocrystals of an areal density in the 1011 cm-2 range) that are chemical vapor or aerogel deposited on the injection oxide. For the quantum-dot memory, this is a polycrystalline island patterned at the intersection of the gate and the channel line. Electrons stored on the island screen the charge in the channel and hence lead to less channel charge for the same applied gate-to-channel potential. This is effectively a change in the threshold voltage. The biggest implication of the scaling of the floating gate region is that the number of electrons used in the device structure is discrete and small. But, this discreteness, or quantization, is not used directly in the device operation. Instead, it is coupled to the channel of the device, thus forming a gain cell. That is, these electrons trapped on the islands influence the conduction of a channel underneath them, and thus the conduction of the channel is a measure of the storage of the electrons. Barriers, used for storage of the electrons, are thus important to the write, erase, and the refresh conditions. But, read of the device, and the amount of signal delivered by the device, are related to the field-effect. The single-electron effects, or the quantum effects, provide a perturbation to it that are detected through the influence of immobile charge on mobile charge.
The device behaves as a gain cell and it is limited in size by field-effect. So, limits of fieldeffect devices are equally important to limits of the floating-gate memory implementations. For a nanocrystal density of vnxt of size tnxt, a tunneling injection oxide of tinj, a control oxide of tcntl, and v average number of electrons per nanocrystal, the threshold voltage is approximately given by:
The spacing between the nanocrystals should be less than the screening length in order to minimize percolative transport in the channel underneath. Figure 8.7 shows, low bias harged conditions (away from the completely discharged and charged branches), that are evidence of this percolation. The oxide in between the nanocrystals is kept large enough to suppress transport directly between the nanocrystals since leakage and subsequent loss to source and drain regions is one of the major methods for loss of charge in floating-gate structures. The control oxide is designed to be thick enough (7 to 15 nm) so that the only path for electron transport to and from the nanocrystals is from the silicon underneathinversion channel region during injection and depletion region during ejection. The barrier height of Si/SiO2 interface is large (~3.15 eV). Oxide thicknesses in the 1- to 10-nm range controls the transmission efficiency over nearly 20 decades. This allows the memories to be made volatile and high speed using small injection oxide thickness or nonvolatile and slower speed using large injection oxide thickness. Table 8.1 summarizes a number of characteristics for the polysilicon/control oxide/silicon island/injection oxide/silicon gate stack. This is an approximate calculation meant to point out the main characteristics of the system. The capacitance (C) is the self-capacitance of the silicon dot used in the calculation of the charging energy (Ec). These vary linearly (for capacitance) and inverse linearly (for energy) with dimension. The quantization effect of confinement in energy (E0) varies as the inverse square of the dimension. At dimensions below 10 nm, the capacitance is small enough that it requires energy of the order of room temperature thermal energy to place an electron on the silicon island. As the dimension decreases further, the eigenenergy of the confined states allowed become larger than the single-electron electrostatic charging energy. When a single electron is stored on the island, it causes the channel threshold voltage to shift by a magnitude that is inversely controlled by the capacitance Ccntl. The shift should not exceed the operating voltages of the structure. Thus, dimensions of between 10 and 3 nm are usable and provide a substantial and observable effect. In the case of nanocrystal and quantum-dot memories, the coupling capacitance to the channel is made to be significantly larger, with additional coupling to the other nanocrystals in the vicinity and, in particular, for the end nanocrystals there is stronger coupling to the source and drain reservoirs. The latter is not surprising; it is one of the major mechanisms for leakage of charge in floating-gate memories. While these results are secondarily geometry specific (e.g., box, sphere, and hemisphere shapes) because of the different degree of confinement, the estimates of capacitance described are within 20% of the more sophisticated calculations. The coupling capacitances to the channel and source and drain regions, therefore, have a stronger influence on the characteristics.
LIMITS DUE TO TUNNELING
Tunneling in Oxide
At small dimensions, two regions of tunneling are important: oxide tunneling (injection and control oxides) which determines the competing balance between injection and ejection, and between source and drain which determines the smallest limit of the device. Figure 8.16 shows the calculated tunneling current.28 As oxide thickness decreases, a large current density can be obtained through thin barriers. Indeed, a 0.15 nm change in oxide thickness leads to a current density change by a factor of 10. Note that a larger roughness arises from the top polysilicon gate/SiO2 interface whereas the bottom surface is nearly atomically smooth. Random effects should be expected from the random gate control capacitance and dopant activation in this polysilicon/oxide region.
Tunneling in Silicon
With a bandgap of 1.1 eV and a low transverse effective mass (0.19 m0, Bohr radius ~ 3 to 4 nm), tunneling between the source/drain regions and the substrate, and from the source to the drain, becomes significant when the distance scales are ~10 nm. For bulk nMOSFET structures, interband tunneling appears when acceptor doping in channel- or halo-doped regions approaches 2 × 1019 cm-3. This tunneling occurs at the source junction and at the reverse-biased drain-substrate junction, and is a standby power constraint similar in nature to that from oxide thickness. In thin silicon structures, interband tunneling (conduction to valence band and back) is avoided if the threshold voltage of the device allows VD+(VG- VT)<Eg/e, a condition that prevents tunneling at the drain end, and is equivalent to the threshold voltage not exceeding ~ 0.55 eV for 0.5-V drain bias. This threshold voltage is consistent with requirements of low subthreshold leakage currents for designs with good subthreshold swing. So, intraband tunneling between source and drain through the channel barrier is a fundamental constraint for adequate field-effect operation and needs to be satisfied in the quantum-dot memory. Figure 8.17 shows tunneling current between source and drain, for a 5-nm-thick sliver of silicon (junctions box doped 5 × 1018 cm-3 and 10 nm apart) for a quasi two-dimensional self-consistent Schrödinger- Poisson calculation. The longitudinal masses of the doubly degenerate ellipsoids form the lowest energy ladder with the smaller transverse mass available for tunneling. The fourfold degenerate in-plane ellipsoids cause tunneling through the longitudinal mass. Tunneling from the doubly degenerate states dominates. This tunneling current, between source and drain, establishes a fundamental constraint of 10 nm for channel length, where the field effect is not subsumed by tunnel effect, and is a practical constraint at which the standby current caused by tunneling leads to too high a standby power drain during chip operation. Geometries such as the straddle-gate structure29 can satisfy this constraint while allowing for a small enough
quantum dot. Table 8.2 summarizes some of these constraints in the design of field-effect structures. In addition to the transistors, these issues also constrain the floating-gatebased
HISTORY: SINGLE-ELECTRON DEVICES TO SESO
A SESO transistor is a nanoscale thin-film transistor, in which bandgap-enlarged nanosilicon film is used as the active channel region.1 Nanosilicon thin-film transistors have been studied in the 1990s as a basic test structure to explore the possibility of single-electron devices,2–12 that is, single-electron memories,3–10 single-electron transistors,11 and single-electron transfer devices.12 A major difference between the structures used in these single-electron devices experiments and SESO transistor is the uniformity of the nanosilicon film. In singleelectron devices, nanosilicon film is intentionally formed rugged, namely, the thickness is different from one site to the other. This is because the ruggedness is intended to create very deep potential energy differences for an electron, resulting in naturally formed nanodots and nanowires. The basic operations of these nanosilicon single-electron devices are as follows3: the structure is a thin-film transistor. One special feature is the channel region is ultrathin: the test device typically used 3-nm silicon film for channel. In addition, the film is intentionally formed granularly to introduce random quantum-confinement potential. This is because to operate a single-electron device at room temperature, one needs to use 10-nm dot; however, lithography to achieve sub-10-nm size is yet to come in 2030 or later. The temperature requirements for single-electron device operations or Coulomb blockade is as follows: kT < q2/(2Ctt), where k is the Boltzmann constant, q is the electron charge, and Ctt is the total capacitance of a dot. By using the natural nano-Grand-Canyon-like structure, one can make nanowire and nanodots without using nanolithography. For example, by setting the gate voltage at an appropriate level near the threshold voltage of the transistor, a narrow percolation channel between source and drain is formed. This condition is used in the first room-temperature operation of a single-electron transistor. 3,4 When one raises the gate voltage further, an electron is injected into an isolated dot, which raises the potential energy for an electron through source-to-drain. By using this dot as a storage dot, one can achieve single-electron memory. After an electron is injected into a dot, one can read out the single-electron charge by the current difference between source and drain. One interesting feature of this device is that the current change is quantized because of the number of the stored electrons is an integer. The author and a coworker Ishii found in these single-electron device experiments that the leakage current of the test devices is unexpectedly low, despite their polycrystalline structure. This low leakage is naturally explained by the quantum confinement model. After this early-stage work, the authors built SESO to confirm the effect as shown in the following sections.
PLEDTR enables the construction of a high-density memory because each memory cell occupies the area of just one transistor, as shown in Figure 10.15. A PLEDTR is stacked onto the gate of a conventional MOSFET with a built-in coupling capacitor to realize a memory cell. High-speed write is possible by transferring electrons from the top electrode (bit line) onto the memory node through the ON-state PLEDTR. Since the OFF-state PLEDTR can confine electrons very effectively, the stored information can be kept for a long time without a refresh operation. Since the information is read via the current in a MOSFET, this cell has gain and a large S/N ratio.
Standby, read, and write cycles are all controlled by voltage VW on the word line, VW (S) (–2V), VW (R) (0.5V), and VW (W) (3V), respectively (Figure 10.16). The generation of negative word line voltage is described in Reference 18. In the standby cycle the built-in coupling capacitor CC causes the memory node voltage VN to be lower than the threshold voltage Vth of the sense MOSFET. In the read cycle VN becomes higher than Vth when the memory state is high, and lower than Vth when the memory state is low. In the write cycle the PLEDTR is opened, and VN becomes the bit line voltage, 1.5 V for the high memory state and 0 V for the low memory state. Figure 10.16(b) and (c) show the results of a mixed-level device and circuit simulation of two memory cells designed using 0.13 μm design rule. A sequence of writing high state (WH), standby (S), read (R), refresh (r), S, R, writing low state (WL), S, R, r, S, R, with 10 nsec/20 ns/5 nsec standby (pre-charge) /read/write time is simulated. VDD = 1.5 V. VW2 is kept at –2 V (unselected) after writing high or low state. The refresh inverts the memory state. The inverting cell concept is described in Reference 19. Although the drain-source current in the ON state of a PLEDTR is small, around 1 μA, high-speed write can be realized because of the reduced stored charge, which is determined by the gate capacitance of the sense MOSFET and estimated as 0.2 to 0.3 fC. On the other hand a high ON current is available from the sense MOSFET to drive the bit line capacitance, 200 fF in this simulation. The memory node voltage VN in the standby and read cycles was calculated as a function of the coupling capacitance CC in Figure 10.17. VH (R) and VL (R) are, in the read cycle, in high and low memory states, respectively. VH (S) and VL (S) are in the standby cycle. The voltage difference on the memory node between high and low memory states, VH – VL, can be larger than the writing voltage difference, 1.5 V in this case, because of the change of memory node capacitance between inversion and depletion states of the sense MOSFET. Random read access in a cell array is possible when Vth is set inside the hatched area, for example, between 0.5 V and –0.5 V at a coupling capacitance of 0.04 fF. This coupling capacitance can be realized for a 50-nm-thick memory node (tN), without needing to form an additional capacitor.
FULLY DEPLETED SOI
The next more complex exploratory device approach is the fully depleted SOI (FDSOI) MOSFET, illustrated in Figure 2.6(b) reveals that FD-SOI is very similar to PD-SOI except that the Si layer is much thinner. To guarantee that the layer remains fully depleted6 and to maintain adequate shortchannel control,23,24 the Si layer should be less than about half the depletion depth of a corresponding bulk device. Advantages of FD-SOI over PD-SOI include elimination of the floating body effect, making circuit design easier, and reduction of the drain capacitance because the depth of the drain-to-body junction is greatly reduced. The subthreshold slope is also mproved, making possible further scaling of VT and VDD. For example, experiments on 50-nm-gate-length FD-SOI devices showed a subthreshold swing of 75 mV/decade (versus 85 to 90 mV/decade for bulk control samples).25 Recent experiments on ultrathin SOI layers have probed the limits of FD-SOI scaling by fabricating both nFETs and pFETs with gate lengths below 10 nm, and with SOI thickness down to 4 nm.26,27 As an example, the 6-nm pFET results are shown in Figure 2.7. Although the IV curves are degraded somewhat due to short channel effects and source/drain resistance, these extremely short devices are still demonstrating good FET behavior.
Problems associated with FD-SOI include the difficulty of controlling the thickness of the very thin Si layers, leading to difficulty in controlling the threshold voltage (which depends on the Si thickness), and the difficulty of achieving low resistance source and drain contacts to such thin Si layers. This latter problem may be overcome through a raised source/drain process, as shown in the excellent results of Chau et al.25 Another concern, which carries over from PD-SOI, is self-heating because of the low thermal conductivity of SiO2. Heat generated in the drain of the FET can cause the device to become so hot that its mobility is significantly degraded.
CONCEPT OF EJ-MOSFETS
According to the scaling principle, the vertical size of a device should be scaled in accordance with the scaling of its lateral size. The reduction of the junction depth is one of the key problems in the vertical scaling of devices; another one is the reduction of the thickness of the gate dielectric. According to the ITRS, a junction depth of at least 5 nm is needed for 10-nm generation, but this depth is hard to obtain with current doping technologies. The idea of electrically induced junctions is attractive for reducing the junction depth. The idea was first implemented in ILD-MOSFETs (MOSFETs using an inversion layer as the source/drain).9 Figure 3.5 shows a schematic illustration of an ILD-MOSFET. The ILD-MOSFET has conductive subgates adjacent to the main gate to induce junctions. As shown in Figure 3.6, short-channel effects can be significantly suppressed around the main-gate-length of 100 nm. This result is understandable because the electrically induced junction is extremely shallow (typically 5 nm) and can cover even sub-10-nm generation. In light of this background, an electrically variable shallow junction MOSFET(EJ-MOSFET) was proposed.10 Figure 3.7 shows a schematic illustration of an EJMOSFET. The EJ-MOSFET has two gates: a lower gate and an upper gate. These gates are insulated from each other with an intergate-oxide layer. The upper gate electrically induces the inversion layers that are self-aligned to the lower gate, and the lower gate controls the current between the inversion layers. Since the structure comprising the lower gate and the two inversion layers is electrically equivalent to a MOSFET, we hereafter refer to the inversion layers as "source/drain junctions." Figure 3.8 shows the calculated depth distribution of the carrier concentration in the source/drain junctions. The distribution is obtained by numerically coupling a Shrödinger equation and a Poisson equation. The junction depth, xj, is extremely shallow (4.5 nm) and can cover the sub-10-nm generation according to ITRS. Although the EJ-MOSFET is designed to emulate conventional MOSFET operations, there are several differences in operation between EJ-MOSFETs and conventional MOSFETs. First, the carrier distribution in the junctions is affected by lower-gate and drain biases because source/drain regions are not actually doped but electrically induced. In order to reduce these effects, the upper-gate bias should be as high as possible. Second, the EJ-MOSFET has a large coupling capacitance between the lower and upper gates due to the thin intergate oxide layer (20 nm). The large capacitance limits the high-speed AC operation of the EJ-MOSFETs. Hence, the device should be operated under DC-bias conditions.
FUTURE TRENDS IN POST-6-NM MOSFETSB
Until now, the scaling limit of MOSFETs has been studied on the assumption that devices are formed on the surface of the (100)-oriented silicon substrates. Now we would like to discuss the feasibility of further scaling of MOSFETs by eliminating that assumption. There are two strategies for improving the performance of post-6-nm devices. One is by enhancing the carrier mobility by suppressing the carrier scattering, and the other is by suppressing the tunneling probability by increasing the effective mass of carriers. The first one makes it possible to improve the device performance without scaling down the device itself. The second one enables further scaling of the devices by reducing direct source-drain tunneling. However, the second strategy is not as effective as the first one because an increase in the effective mass reduces the carrier mobility. Hence, only the first strategy is discussed here. Strained silicon technology is a promising technology for reducing carrier scattering. 19–21 When the silicon is epitaxially grown on a SixGe1-x substrate, tensile strain is introduced, and it gives rise to a valley splitting in the conduction and valence bands. As a result, the carrier concentration in the lower energy states (the lowerenergy valley in the conduction band and the lower-energy valence band) reduces the carrier scattering and, consequently, enhances the carrier mobility. An enhancement of several tens of percentage points has been demonstrated experimentally. However, since the lower-energy states have a smaller effective mass than the higherenergy states, the carrier concentration in the lower-energy states leads to an increase in the direct source-drain tunneling currents to the tune of several tens of percentage points. To avoid this problem, the gate should be made slightly longer because the tunneling current depends drastically on the barrier width. As shown in Figure 3.25, an increase in the tunneling current of several tens of percentage points can be easily avoided by increasing the barrier width by as little as 0.5 nm, which does not significantly reduce the drain current because the drain current linearly (or more weakly in the ballistic transport regime) depends on the barrier width. The quantum-wire transistor is another candidate for suppressing carrier scattering.
22 Because carrier scattering is limited to the one-dimensional direction, the scattering rate can be significantly reduced. However, an enhancement in mobility has not been demonstrated yet. This is probably because the fabrication method of quantum wires has not been fully developed. The development of damage-free fabrication techniques for uniform wire structures may improve the carrier mobility.
Quantum Effects in
The size of silicon metal oxide semiconductor field-effect-transistors (MOSFETs) in very large scale integrated ciruits (VLSIs) has been miniaturized for over 30 years in order to attain higher performance and higher integration. The gate length of the state-of-the-art complementary MOSFET (CMOS) devices has reached less than 60 nm, and the most advanced MOSFETs in the research level have the gate length less than 10 nm.1,2 As the horizontal dimensions such as gate length are scaled down, the vertical dimensions such as gate dielectric thickness and depletion layer thickness have been also rapidly scaled down to suppress the short channel effect. Thus, the carriers in advanced MOSFETs are strongly confined vertically, resulting in the quantum confinement effect.
Although the quantum effects and their device applications have been widely studied in the field of compound semiconductors, it is generally recognized in the field of silicon devices that the quantum effects are not favorable effects. This is mainly because the quantum effects are usually very sensitive to device size, and thus, the small distribution of the device size will result in large variation in the device characteristics when the quantum effect dominantly affects the device performances. Moreover, the tunneling current that is caused by the quantum effect rapidly increases when the thickness of gate dielectrics becomes less than 2 nm, which results in the exponential increase in standby power dissipation. It is also well known that the drive current in MOSFETs with very thin gate insulator will not be improved due to the finite thickness of electron inversion layer that is also induced by the quantum effect. Therefore, suppressing these kinds of quantum effects have been the device design guideline of advanced MOSFETs. However, the device size
has now reached the nano-scale regime. The quantum effects will certainly take place and affect the device characteristics and they cannot be considered negligible any more. It is very important to positively utilize the quantum effects and take the quantum effects into consideration in the design of silicon nano-scale devices.
In this chapter, quantum effects in silicon nanodevices are described. First, the basic understanding of the band structure and quantum confinement effects in silicon are described. Next, the researches on the observation and analysis of quantum effects in MOSFETs are reviewed. Then, characteristics of ultranarrow-channel MOSFETs that exhibit stronger quantum effects than usual MOSFETs are described. More focus is placed on the positive utilization of the quantum effects that will enhance the device performance and will possibly break the fundamental scaling limit of silicon MOSFETs.