SMALL MOSFETS
The MOSFET is created when the electric field between the gate and the semiconductor is such that an inverted carrier population is created and forms a conducting channel. This channel extends between the source and drain regions, and the transport through this channel is modulated by the gate potential. This much has been known since the first descriptive patent on the topic. Indeed, the operation of the MOSFET is almost exactly as described in a simple one-dimensional semiclassical treatment, and this approach has been modified and adapted continuously over the past few decades. However, it has become understood that there is quantization in the basic MOSFET, even for quite large gate lengths. This is because the gate field pulls the inversion channel carriers quite close to the oxide-semiconductor interface, and these carriers are confined between this interface and the potential in the bulk. This confinement is sufficient to cause quantization to occur in the direction normal to the oxide-semiconductor interface. This quantization leads to a quasi-two-dimensional carrier gas in the plane of the channel. While this effect is quite important, it is equally important to understand that the transport is in the plane of this quantized layer, and so is not directly affected by this quantization. We will discuss this in more detail in a subsequent section.
As the channel length has gotten smaller, there has been considerable effort to incorporate a variety of new effects into the simple (as well as the more complex) models. These include short-channel effects, narrow width effects, degradation of the mobility due to surface scattering, hot carrier effects, and velocity overshoot. However, as gate lengths have become less than ca. 100 nm, the issue is becoming one of ballistic transport rather than these other problems. By ballistic transport, we refer to the situation in which the channel length is less than the mean-free path of the carriers, so that very little scattering occurs within the channel itself. If we take the thermal velocity of a carrier in Si as 2.5 × 107 cm/s at room temperature, a channel mobility of 300 cm2/Vs leads to a relaxation time of 5 × 10-14 sec and a mean-free path of the order of 12 × 10-7 cm, or 12 nm. Thus, we might expect only a few scattering events in a channel length of 20 to -30 nm. While this is a very crude approximation, it points out that the properties of the carriers in these very small devices will be quite different than those in larger devices. In this case, the "theory" of the device is actually much closer to that of the simple approach discussed in the Simple One-Dimensional Theory section, at least in conceptual detail. For this reason, we will review some simple interpretations of the onedimensional current equation, and then develop the ballistic device theory. This becomes important, because the same intuitive ideas carry over to the Landauer formula,15 which is often invoked in pure quantum transport situations.
Practical CMOS Scaling
CMOS TECHNOLOGY OVERVIEW - CURRENT CMOS DEVICE TECHNOLOGY
Figure 2.1 illustrates most of the important features of state-of-the-art conventionalbulk CMOS technology. The gates are n- and p-type polysilicon, and are toppedwith a metal silicide, which lowers the gate series resistance. The gates are patterned down to minimum dimensions that are 50% or more below the general lithographic feature size by means of special lithographic and lateral etching techniques. The gate dielectrics can be as thin as 1.0 nm of Si oxynitride for high performance logic. Scaling demands these thin gate insulators in order to keep short channel effects under control and to maximize performance, but tunneling leakage current through these thin insulators has become a major concern for many applications. Shallow trench isolation (STI) is used to separate the FETs, resulting in very high circuit density. A combination of deep and shallow implants are used for the source and drains, and these must be carefully engineered to reduce short channel effects, prevent gate insulator degradation due to hot electrons and provide low contact resistance between the FET channel and the silicide contacts. The doping profiles in the channel are also very important. Shallow angled ion implants are used to create so-called "halo" doping profiles that are higher near the source and drain and lower in the middle of the channel. Since the halos are defined relative to the edges of the gates, the average doping in the halo overlap region increases when the gate length shrinks. This doping increase tends to compensate for the natural decrease of threshold voltage (VT) that occurs in very short MOSFETs, enabling the use of FETs with shorter gate lengths than would otherwise be possible. Although the wiring is not shown in Figure 2.1, it is clearly essential for creating large integrated circuits. Today most of the wire is copper because of its low resistivity and reduced electromigration. Wire-to-wire capacitance is reduced by the use of fluorinated silicate glass (FSG) or organosilicate glass (OSG) for the insulator, with permittivity (k) ranging from 3.7 down to 3.0, and even lower k materials may be in use soon. To keep wire delay under control, a hierarchy of wiring sizes is usually used, from very fine wires at minimum lithographic dimension on the bottom to large "fat" wires on the top. Partially depleted silicon-on-insulator (PD-SOI) CMOS, shown in Figure 2.2, is also available. It is very similar to bulk CMOS, the main difference being that PD-SOI MOSFETs are fabricated in a thin layer of Si, ~150 nm thick, on top of an insulating SiO2 layer. In partially depleted SOI, the depletion region in the FET channel is thinner than the silicon layer, leaving some undepleted silicon which acts as a floating body for the FET. The buried oxide (BOX) layer is typically 150 to 250 nm thick and completely insulates the device layer from the substrate. This construction results in source- and drain-to-body junction capacitances that are significantly reduced, which can increase digital switching speed. The floating body eliminates the usual bulk MOSFET body-effect dependencies on source-tosubstrate voltage, enhancing some types of circuitry. On the other hand, there are other floating-body effects such as history-dependent body bias and increased output conductance (caused by the injection of majority carriers into the body by impact ionization in the drain region) that may degrade the performance of some circuits.
}FIGURE 2.1. Conventional Bulk CMOS cross-sectional diagram (from Ref. 7, reproduced with permission. Copyright 2002, Kluwer.)
FIGURE 2.2 PD-SOI CMOS technology cross-sectional diagram (from Ref. 7, reproduced with permission. Copyright 2002, Kluwer.)
The Scaling Limit of MOSFETs
There are many effects that tend to limit scaling, but for the sake of discussion we can divide them into four categories: quantum mechanical, atomistic, hermodynamic, and practical.
-QUANTUM MECHANICS
Quantum mechanical scaling limitations include both confinement effects and tunneling effects. Confinement effects occur when electron or hole wavefunctions are squeezed into narrow spaces between barriers. In FETs this primarily happens in the channel, where the charges are squeezed between the gate insulator on one side and the built-in field of the body on the other side. Quantum confinement in this approximately triangular well raises the ground state energy of the electrons or holes, which increases the threshold voltage, and shifts the mean position of the carriers a little farther from the Si-SiO2 interface. This shift weakens the effect of gate insulator scaling by adding 0.5 to 1.5 nm to the effective oxide thickness, depending inversely on inversion charge density and built-in field. The quantum mechanical ground state energy rise is particularly of concern for potential future SOI FETs with extremely thin bodies (e.g., <5 nm). In such devices the ground state, and hence the VT, varies inversely with the square of the Si layer thickness. Uncertainty in the layer thickness is expected to translate into large uncertainty in VT. Quantum mechanical tunneling is generally more detrimental to scaling than the confinement effects. When electrons or holes tunnel through the barriers of the FET, it causes leakage current. As scaling continues, this ultimately causes unacceptable increases in power dissipation. The leakage may also cause some types of dynamic logic circuits to lose their logic state, but the former problem usually seems to arise first. There are primarily two forms of tunneling leakage: tunneling current through the gate insulator, and tunneling current through the drain-to-body junction. The first of these is the most prominent and well-known problem. Figure 2.10 illustrates the dependence of these currents on voltage and oxide thickness. In nFETs this current is primarily due to the tunneling of electrons from the channel into the gate. In pFETs with very thin insulators (<1.5 nm) the tunneling current at low voltages can be caused by hole tunneling from channel to gate, but at higher bias it is usually due to the tunneling of electrons from the valence band of the gate into the conduction band of the body. The processes differ because the conduction band barrier is only ~3.5 eV, while the valence band barrier height is ~4.5 eV. In accordance with the simple Wentzel-Kramers-Brillouin (WKB) approximation, tunneling current generally varies exponentially as
where d0 = 0.1, m* is the effective mass in the barrier in units of the electron mass, and Eeff is the bias-dependent effective barrier height in eV. Clearly, the insulator thickness cannot be scaled too thin without causing excessive tunneling current. To circumvent this limit on scaling, the industry hopes to use a higher dielectric constant ("high-k") insulator instead of using a thinner insulator. This does not result in perfect scaling, but as can be seen from the scale length derived in Equation (2.1) and Equation (2.2), it may work well enough to be useful. Unfortunately, higher permittivity insulators tend to have lower bandgaps and lower barrier heights. What is needed is a material with fairly high permittivity and not too low a bandgap, so that one can obtain lower leakage current at the same capacitance per unit area. High-k replacements for SiO2 must also satisfy many other requirements, including thermal stability relative to Si at the necessary high processing temperatures, low diffusion constants, sufficiently matched thermal expansion, and low interface trap density. A significant problem for most of the promising high-k insulators for FETs is that they generally cause the channel mobility to be degraded. It is not yet clear how this can be overcome. To date, the only successful "high-k" insulators are Si oxynitride composites, with k ~ 5 to 6, but HfO2 (k ~ 20) and Hf silicates (k ~ 10) are presently considered promising. The use of metal gates in conjunction with high-k insulators presents interesting possibilities. It allows increased capacitance by eliminating depletion of the polySi gate, while at the same time tending to result in higher threshold voltages due to the tendency for most metals to display roughly midgap workfunctions. Band-to-band tunneling between the body and drain of an FET is the second important source of tunneling leakage current. This occurs when the FET is in the "off" state, with high drain voltage and low gate voltage. Since the gate potential can significantly modulate this current, it is often referred to as GIDL (gate-induced drain leakage). Recent measurements have shown that band-to-band current varies as , e(-dB2B /landa) where dB2B is the minimum physical distance from a point in the conduction band to a point in the valence band at the same energy, and landa = 0.38 nm is the characteristic length scale for the tunneling. These experiments suggest that this form of tunneling will become a significant cause of power dissipation when the body doping reaches the 1019 cm-3 regime. Since direct band-to-band tunneling depends on conduction band states being lined up with valence band states, it may be avoided by arranging the body and drain potentials so that the bands never line up. In bulk MOSFETs this might be accomplished by forward biasing the body, which might be an interesting option at low temperature,4 but it is unlikely that it would be applied to anything except very high-performance computing.
FIGURE 2.10 Calculated (lines) and measured (dots) results for tunnel currents from inversion layers through thin oxides. (Adapted from Lo et al. From Ref. 6, reproduced with permission. Copyright 1999 IEEE.)
-ATOMISTIC EFFECTS
The atomistic effects that cause limitations to scaling are those in which the discreteness of matter gives rise to large statistical variations in small devices. These statistical variations occur because the atoms or molecules tend to display Poisson statistics in their number or position, and the Poisson distribution for small numbers can become very wide. Wide distributions are the exact opposite of what is needed to successfully manufacture extremely large-scale integrated circuits. There are at least three major concerns in this area: the discreteness of dopant atoms, interface roughness at the Si-SiO2 interface, and line edge roughness (LER), which is also partly related to the discreteness of energy (photons). The discrete doping problem has probably received the most attention. The difficulty is that although the average concentration of doping is quite well controlled by the usual ion implantation and annealing processes, these processes do not control the exact placement of each dopant. This results in randomness at the atomic scale, which causes spatial fluctuations in the local doping concentration, resulting in device-to-device variation in MOSFET threshold voltages. The uncertainty in the number of dopants, N, in any given device is expected to vary as sqr(N), in keeping with Poisson statistics, so that the fractional uncertainty and, hence, the threshold variation, FiVT, may become quite large. In addition, the uncertainty in the placement of the dopants creates additional VT uncertainty of a similar magnitude. Furthermore, since FiVT varies as 1/sqr(width), narrow devices such as those in static random access memory (SRAM) cells are most affected by this effect. Current generation SRAM devices are already approaching the point of having only a few hundred dopant atoms controlling the threshold voltage, and the resulting FiVT is expected to make the design of robust SRAMs increasingly difficult. This problem is compounded by the large number of devices in an SRAM, which can cause the statistical tail to extend to more than 5 sigma.
The effects of doping fluctuations on MOSFETs have been investigated by many workers, both experimentally and via modeling. The most quantitatively accurate
modeling results use randomly placed dopants in full three-dimensional (3-D) MOSFET simulations to fully resolve the effects of dopant number and placement. An example of such a calculation is shown in Figure 2.11, which reveals the wide variation in subthreshold behavior that is expected in an aggressively scaled 11-nm bulk MOSFET due to random dopant placement. Although these variations are quite large, there are several methods that might be used to reduce the variation. The most straightforward approach for bulk devices is to move the dopants in the body back away from the surface using highly retrograde channel doping profiles. Simulations show that such profiles can lower FiVT up to 2× compared to uniformly doped channels. The best way to eliminate these fluctuations is to remove the doping, which may be possible in ultra-thin SOI or double-gate FETs using a metal gate workfunction to set VT, rather than doping.
The second atomistic effect of concern regarding scaling is the atomic roughness of the interface between the Si channel and the SiO2 gate insulator. The somewhat random character of the bonds in the amorphous SiO2 causes atomic-scale variations in the position of the surface. In addition to causing random VT variations in small devices, this roughness causes extra scattering of the carriers in an inversion layer, decreasing the mobility and hence the drive current of an FET. The problem isexacerbated at the higher oxide fields that are reached in more highly scaled devices. When the silicon layer is made extremely thin (<5 nm), with oxide layers on both sides, these atomic variations combine with the quantum confinement effect to cause significant scattering and a rapid loss of mobility. Finally, high-resolution 3-Dnumerical simulations have shown that these atomic thickness variations also cause increased threshold voltage variation. The third atomistic effect is line edge roughness (LER). Discrete molecular effects in the photoresist exposure and development cause unevenness on the edges of patterns, an example of which is shown in Figure 2.12. When this pattern is then etched (e.g., by reactive ion etching) into an underlying structure, the molecular randomness of the etch may still further increase this roughness. This is particularly problematic for the gates of aggressively scaled MOSFETs, since they are usually overetched in some way to make the gate length smaller than the nominal lithographic dimension. This etching of the gate does not, however, reduce LER (but may increase it), with the result that the random variation in gate length of the FET may become quite significant. Some 3-D simulations of this effect have shown that it leads to still further threshold voltage variation, as shown in Figure 2.13. Since the origin of LER is in the discrete molecular composition and interactions of the resist, it is an open research question as to how much it can be reduced. Furthermore, as lithography moves toward shorter-wavelength, higher-energy light sources, the quantization of photons may also come into play, as fewer photons are required to expose minimum size features, leading to more statistical variation in the number of photons actually received.
FIGURE 2.11 Simulated IV curves for 100 different 11-nm channel length bulk MOSFETs with discretely placed dopants. Each grey curve corresponds to a different random placement of the dopants, derived in a Monte Carlo manner from the designed average doping profiles. The solid black line is the geometric average of the 100 curves, and the dashed line is the IV curve expected from continuum doping profiles. (From Ref. 15, reproduced with permission. Copyright 2002 IBM.)
FIGURE 2.12 Example of line edge roughness (LER). Inset shows a micrograph of 100-nm EUV lines and their edges. Main plot shows the autocorrelation function of these edges, along with a Gaussian and an exponential fit. (From Ref. 69, reproduced by permission. Copyright 2003, IEEE.)
FIGURE 2.13 Threshold voltage uncertainty versus rms magnitude of the line edge roughness for 30 × 50 and 50 × 50 nm MOSFETs at VDS = 1.0 V (squares) and VDS = 0.1 V (circles). (From Ref. 69, reproduced by permission. Copyright 2003, IEEE.)
-THERMODYNAMIC EFFECTS
Thermodynamics is just as significant in limiting scaling as the preceding effects. The first way it limits scaling is in its control of the subthreshold behavior of MOSFETs. The subthreshold current of a MOSFET originates in the high-energy tail of the statistical distribution of carriers in its source region. The carriers in the source are governed by Fermi-Dirac statistics, and so the tail of the distribution is essentially Boltzmann. Only the carriers with high enough energy to pass over the channel barrier are eligible to become drain current, and so the subthreshold current varies exponentially with gate voltage as
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Libro "SILICON NANOELECTRONICS"
Edited by "Shunri Oda • David Ferry"
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