QUANTUM EFFECTS IN MOSFETS
BAND STRUCTURES OF SILICON
The lowest points in the conduction band of silicon lie along the Alfa-directions in the Brillouin zone. These points are apart from the center of the zone (R-point) and called X-points. There are six Alfa-directions and, therefore, there are six equivalent minima at X-points in the conduction band of silicon, as shown in Figure 4.1. All the valleys at X-minima are equivalent in terms of energy in bulk silicon. The energy in each valley can be expressed by a parabolic approximation. However, the energy depends on the direction and thus it is anisotropic.
The picture of the valence band is much more complicated than that of the conduction band.4,5 There are three types of holes at R-point in the valence band: the light hole, the heavy hole, and the split-off hole. The light hole and heavy hole are degenerated at the top of the bands, and most of holes are populated in the light and heavy hole hands. The top of the light hole band and the top of heavy hole band are non-parabolic and it is also anisotropic. Figure 4.2 shows a schematic of the light and heavy holes. The energy difference of the light/heavy holes and the splitoff hole is 44 meV. The split-off hole band cannot be ignored at room temperature, because the splitting energy is comparable with the thermal energy at room temperature.
SURFACE QUANTIZATION
Figure 4.3 shows a schematic diagram of the conduction band in MOS structure of bulk silicon. The Si-SiO2 interface is inverted by the gate bias and electrons are populated at the interface. When the impurity concentration in the channel is high, which is often the case in advanced MOSFETs, potential slope near the interface is so steep that electrons in the inversion layer are confined by gate oxide and the steep potential slope. The electron energy perpendicular to the interface is now quantized into discrete states (en). Please note that the total energy (En) is not quantized because electrons are not quantized in parallel to the interface.
Each state (referenced by n) forms a subband. The ground state energy rises from the conduction band edge as shown in Figure 4.3. This phenomenon is called surface quantization. Higher gate voltage is required to invert the Si-SiO2 interface under the surface quantization, which results in the increase in threshold voltage. Therefore, threshold voltage increases as the impurity concentration increases.
The surface quantization also takes place for holes. The fall in the ground state energy in the valence band leads to the decrease in threshold voltage. However, the decrease in threshold voltage corresponds to the increase in threshold voltage in the absolute value in p-type MOSFET. The rise in the ground state in the conduction band and the fall in the ground state in the valence band results in the effective bandgap widening. The surface quantization is often expressed by a triangular well approximation. Although the triangular well approximation is a simple model, it is highly reliable. This is because the potential near the interface is almost a triangular shape, and the potential barrier of SiO2 is relatively high in silicon MOS structure. Some of the models of the surface quantization are based on the triangular well approximation.
The confinement energy depends on the effective mass perpendicular to the Si-SiO2 interface. Since the six equivalent valleys in the conduction band are anisotropic, the valleys split into two sets of valleys in energy as shown in Figure 4.4. Here, (100) plane is assumed for the Si-SiO2 interface, which is commonly used in silicon CMOS for VLSI. Now, the valleys are split into twofold degenerate valleys and fourfold degenerate valleys according to the perpendicular masses. Twofold valleys stay at lower energy than fourfold valleys due to higher perpendicular mass. Similarly, energy levels of the light hole band and the heavy hole band in the inversion layer are split.
Ballistic Transport in Silicon Nanostructures
For the past two decades novel transport phenomena in nanometer scale semiconductor structures have been explored along with tremendous progress of nanofabrication and material growth technologies. Both wave and particle natures of electrons have come out in various ways and have brought very unique transport properties to us, which had not been shown by electrons in the micro scale structures. The electric characteristics we usually obtain for the present ultra-large scale integration (ULSI) devices are the statistical average of a large number of electrons (to the order of Avogadro's number) in motion, which suffer from frequent scattering events caused by various mechanisms. Under these circumstances the electric characteristics are described by using macroscopic quantities such as the mobility which is determined mainly by elastic impurity scattering and inelastic phonon scattering. Electrons hardly maintain the memory of the phase of their wave functions as the energy of electrons changes due to the inelastic phonon scattering with the phonon emission/absorption. The motion of electrons is therefore described well as classical particles under the electric fields.
When a device structure, however, is made smaller than the phase coherence length of the electron wave function, the wave nature of electrons should appear, and the effects of the phase of the electron wave function can no longer be neglected. Such a regime is called as a mesoscopic system. The quantum confinement effect in the semiconductor superlattice is one of the examples that results from the electron wave nature. As the elastic scattering does not change the energy of electrons, the phase of electron wave function is maintained, and the associated quantum-mechanical phenomena of electrons are still observed even if the elastic mean free path is shorter than the device dimensions. Reducing the device dimensions further down below the elastic mean free path for impurity scattering, the motion of electrons across the device becomes ballistic. Under these circumstances electrons behave in a manner similar to light propagating in a loss-free waveguide or electrons traveling in vacuum. In a perfect ballistic system the current conduction should be determined purely by the channel geometry (i.e., the boundary of the channel) without any statistical fluctuation caused by randomly distributed dopant atoms. As the disappearance of the conductivity fluctuations has already been observed, ballistic transport is expected to be increasingly important along with further downscaling devices and improving the crystallinity.
In this short review we investigate physics of ballistic transport in Si nanostructures by focusing on the phenomenon of conductance quantization observed for an extremely short and narrow constriction structure called a quantum point contact (QPC). Due to lack of space and time we do not cover ballistic (and quasi-ballistic) transport phenomena expected to occur in MOSFETs by decreasing their dimensions into a few tens of nanometers, which is also an important subject apparently. Section II provides a brief history of research on the conductance quantization in lateral semiconductor QPC structures with a simple theoretical footing for explaining the phenomenon. In Section III we introduce a vertical nano FET structure, which is also a QPC formed in a vertical direction. We discuss device fabrication, observation of the conductance quantization, and the effects of a magnetic field on the conductance characteristics.
SESO Memory Devices
HOW NANOTECHNOLOGIES SOLVE REAL PROBLEMS
The integrated electronics technologies have reached the turning point at around 100 nm for various reasons. Especially, CMOS devices suffer subthreshold leakage and gate leakage problems, which inevitably change the conventional miniaturization and performance enhancement trend of silicon integrated circuits. Although the gate leakage might be surmounted by high-k insulators, which are under intensive investigation, subthreshold leakage is directly related to fundamental Boltzmann statistical physics, and is becoming a very high hurdle to overcome. Under these circumstances, nanodevices, which might go beyond CMOS devices, attract anticipation. However, when one takes "nano" literally, there is a large gap between the anticipation and reality. If we extrapolate the conventional miniaturization trend along "Moore's Law" down to nanometer level, one has to wait until 2030. Moore's law states the integration level of a chip increases by a factor of four every 3 years, which corresponds to 30 percent shrink of minimum feature size.
Here, I believe that nano should not be used to form all the features sizes, rather, partial introduction of nanostructures in the conventional device structures gives much impact on the limitations of conventional CMOS devices (Figure 9.1.) SESO (Single-Electron Shut-Off) memory introduced here is conceived based on this grand vision.
NEW DIRECTION OF ELECTRONICS
Not only does the technical aspect of the pictures drive the change, but also does the market. The volume market that drives the electronics industry has moved from PC to mobile devices. Worldwide cellular phone unit shipment is four times larger than that of PCs, and new demand is been actively added; for example, 2003 was the year of camera on the phone. In the future, ubiquitous computing and networking technologies will flood computers in the entire life and business environments. This mobile-to-ubiquitous direction drives strong requirements for advanced multimedia/broadband processing capabilities and human interfacing capabilities. However, on the other hand, these heavy workloads have to be handled with very limited power budget because of the battery-life restrictions. Particularly, subthreshold, drain-induced barrier lowering, and gate leakages impose serious power problems in the sub-100-nm region.
The bottleneck to overcome the power problem is memory. Even in a processor LSI or a system-on-a-chip (SoC), a majority of transistors are used for memory. The memory-transistor ratio is estimated to increase as we cram more functionality on a chip as found in the ITRS (International Technology Roadmap for Semiconductors) roadmap, in which the memory ratio in a typical SoC will reach as high as 80 percent in 2007 as shown in Figure 9.2. Those massive memory bits will hold large programs for complex software functions and large multimedia data, such as video and audio data. Memory is and will continue to be the dominant cost, power, and performance factors in processors and SoCs. SESO memory is conceived to improve total cost, power, and performance of the sub-100-nm system under the above circumstances.
Few Electron Devices and Memory Circuits
Kazuo Nakazato and Haroon Ahmed
Over the last few decades, the performance of very large scale integrated (VLSI) circuits has been steadily improved by scaling down device dimensions. Today 65- to 90-nm lithography technologies have been introduced in production lines, and the size of a memory cell has been reduced to 0.02 μm2. Two major semiconductor memories have been developed as high-density memories. One is the dynamic random access memory (DRAM), which is characterized by its unlimited number of write cycles and high speed. The other is flash memory characterized by its nonvolatility. Flash memory is rewritable read-only memory (ROM); the write cycles are limited, a block erase operation is needed before writing data, and verification is required to write data. DRAM and flash memories cannot be replaced by each other in applications. DRAMs are used as main memories of computers, and flash memories are used as an alternative to hard disks.
Memory architectures are now approaching fundamental difficulties. In this chapter we discuss the future possibilities for DRAM-type memories. For flash type memories, several new approaches have been proposed such as nanocrystal memories which use nanometer-scale islands instead of a floating gate to store charge. These approaches will be discussed in other chapters of this book. Since the approaches are very different for DRAM and flash memories, we will concentrate our attention on DRAM architecture which has several restrictions such as the need to maintain high speed and low supply voltage.
In section 2 of this chapter we discuss the difficulties of present day DRAMs and consider DRAM gain cells as one of the solutions. In Section 3 the phase-state low-electron number drive memory (PLEDM) is described as a high-density DRAM gain cell. The PLEDM has smaller cell size compared to a current DRAM cell and has scalability; that is, the stored charge can be reduced according to the reduction of the cell size. Further into the future, DRAM gain cells can be single-electron memories, where the precise number of electrons is controlled by multiple-tunnel junctions (MTJ). In the ultimate, single-electron memories can be based on just one electron representing one bit of information.
Single-Electron Logic Devices
Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, and Hiroshi Inokawa
Silicon metal-oxide semiconductor field-effect transistors (MOSFETs) act as simple electrical switches that allow us to build large-scale integrated circuits (LSIs) with very simple architectures. Owing to progress in fabrication technologies, we can now build LSIs that include tremendous numbers of transistors. However, this increase of transistors causes a large power dissipation in a small Si chip, which will limit the further growth of functionality of the LSIs in the not-too-distant future.
To overcome the limitation, we need new functional devices that operate under different principles and dissipate as little power as possible. The progress in fabrication technology has also made it possible to make small structures on the order of nanometer scale. In fact, MOSFETs with the gate lengths of less than 10 nm have already been achieved. This length is small enough to observe quantum size effects even in silicon though the effective masses of carriers are relatively large. We can use the quantum size effects to reduce power consumption and build new functional devices. One simple way to reduce the power consumption is to use single-electron devices (SEDs). SEDs have to have nanometerscale islands because their operation principle uses the Coulomb blockade effect, where the charge repulsion among the electrons confined in a small island plays an important role. The power dissipation of an SED circuit can be reduced because of the controllability of the flow of electrons by means of one-by-one unneling. One of the great advantages of SEDs is that the operation principle is simple and does not require coherency of carriers. We only need small structures to cause charge repulsion. In addition, the operation principle guarantees that the performance of
SEDs will improve as their size is reduced. In contrast, MOSFETs require complicated structures and dopant profiles to ensure their operation as a simple electrical switch as device size is reduced. These two features of SEDs, low power consumption and stable operation in small structures, are the primary requirements for future LSI devices.
Another way to reduce the power consumption is to use the coherency to suppress the voltage loss. If we can transfer electrons or holes coherently, there will be no voltage loss. Some quantum-effect devices using the interference of electron waves have been proposed and tested their fundamental operation at low temperature.
However, the output signal is quite small because of the difficulties in keeping the coherent length much longer than the sample length after attaching complicated electrodes. As a result, it is difficult to use coherency for achieving high performance with low power consumption at present. It is well known that the carrier coherency and quantum size effect in a small semiconductor island, which is the main part of SEDs, is also important for the transport of the carriers. This chapter focuses on device applications for future LSIs.
It is very important for device applications that the operation characteristics of SEDs are quite different from that of conventional MOS or bipolar transistors. This means we have to develop suitable circuits for SEDs. Many kinds of basic singleelectron logic circuits have been proposed and experimentally demonstrated. Some of them perform a simple switching operation like MOS transistors, which is advantageous because we can employ the highly advanced technologies developed for CMOS circuit designs. Although we can use a SED as a simple switch, the Coulomb blockade and one-by-one electron tunneling dominate the current flow in the device. This causes a low drivability, which is the biggest drawback of SEDs. However, SEDs have special features not found in conventional MOSFETs. These features can be exploited to achieve high functionality that will make circuits simple, efficient, and fast.
This chapter discusses the logic circuit applications of SEDs. Section 2 outlines the operation principles and operation characteristics of SEDs and discusses the stability of their operation, which is the most important feature for their practical application. The operation characteristics strongly depend on the base materials and fabrication methods. Section 3 describes some fabrication methods developed for Si SEDs. Section 4 introduces the applications of SEDs to logic circuits. Though their small size is beneficial for high-density memory LSIs, the low-power operation nature and functionality of SEDs are more suitable for logic circuit applications. Some of the applications covered in this section have actually been experimentally demonstrated.
FUENTE:
Libro "SILICON NANOELECTRONICS"
Edited by "Shunri Oda . David Ferry"
Published in 2006 by
CRC Press
Taylor & Francis Group
6000 Broken Sound Parkway NW, Suite 300
Boca Raton, FL 33487-2742
POSTEADO POR:
Jose Ney Gandica Cardenas C.I 18791714
Cursante de CRF
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